1. Field of the Invention
The present invention relates to the implementation of at least one high voltage component and logic circuits in monolithic form.
2. Discussion of the Related Art
High voltage components, such as thyristors, which are frequently used to block voltages higher than 600 V, are generally implemented in semiconductor wafers, one of the layers forming the component substantially corresponding to the thickness of the wafer. Of particular interest are technologies in which the rear or lower surface of the component is uniformly coated with a metallization in direct contact with the semiconductor.
FIG. 1 illustrates an example embodiment of a monolithic structure associating a high voltage component and logic circuits.
This structure is implemented in a semiconductor layer 1, for example, of type N corresponding to the semiconductor substrate. In the right portion 3 of the wafer, a vertical thyristor is shown. On the rear or lower surface side of substrate 1, a P-type region 2 is formed, and on the front or upper surface side a P-type well 4 is formed in which an N-type region 5 is also formed. An anode metallization M1 forms one piece with the rear surface. A cathode metallization M2 covers region 5. A metallization M3 covers a portion of P-type region 4 and forms the cathode gate G of the thyristor. This vertical thyristor is insulated from the remainder of the monolithic structure by a P-type wall 6, generally formed at the beginning of the fabrication process by drive-ins extending from the upper and lower surfaces of the wafer. Reference 7 has been used to designate N.sup.+ -type regions used, conventionally, as channel stops. On the left side of the substrate, insulated from the thyristor by wall 6, several logic components can be formed in a P-type well 8. However, since the rear surface of N-type substrate 1 is coated with metallization M1, this rear surface is likely to be at the highest potential applied to this metallization, for example, a potential of approximately one thousand volts. This imposes a great number of insulation restraints on the components formed in well 8 and makes it very difficult to form components directly within the upper surface of substrate 1.
In the related art various solutions have attempted to improve this situation, and notably, to satisfactorily bias well 8 so that it remains properly insulated from the high voltage.
One conventional solution to solve this problem of insulating the logic portion consists of coating the bottom of the wafer facing the logic portion with an insulating layer over which metallization M1 is then deposited. This technique provides excellent results but is complex to implement and is incompatible with some manufacturing processes.